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INTEGRATED CIRCUITS
DATA SHEET
SAA5284 Multimedia video data acquisition circuit
Objective specification Supersedes data of 1997 Mar 03 File under Integrated Circuits, IC22 1998 Feb 05
Philips Semiconductors
Objective specification
Multimedia video data acquisition circuit
CONTENTS 1 2 3 4 5 6 7 7.1 7.2 8 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10 8.11 8.12 9 10 11 12 13 13.1 13.2 13.3 14 15 15.1 15.2 15.3 15.4 16 17 18 FEATURES GENERAL DESCRIPTION QUICK REFERENCE DATA ORDERING INFORMATION MAIN FUNCTIONAL BLOCKS BLOCK DIAGRAM PINNING INFORMATION Pinning Pin description FUNCTIONAL DESCRIPTION Power supply strategy Clocking strategy Power-on reset Analog switch Analog video-to-data byte converter Packet filtering Packet buffer FIFO Host interface Interrupt support DMA support I2C-bus interface LIMITING VALUES QUALITY & RELIABILITY CHARACTERISTICS TIMING APPLICATION INFORMATION Hardware application circuit for ISA card Hardware application circuit for PCI application Software application information PACKAGE OUTLINE SOLDERING Introduction Reflow soldering Wave soldering Repairing soldered joints DEFINITIONS LIFE SUPPORT APPLICATIONS PURCHASE OF PHILIPS I2C COMPONENTS
SAA5284
1998 Feb 05
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Philips Semiconductors
Objective specification
Multimedia video data acquisition circuit
1 FEATURES
SAA5284
* High performance multi-standard data slicer * IntercastTM (Intel Corporation) compatible * Teletext (WST, Chinese teletext) (625 lines) * Teletext (US teletext, NABTS and MOJI) (525 lines) * Wide Screen Signalling (WSS), Video Programming Signal (VPS) * Closed Caption (Europe, US) * Data broadcast, PDC (packet 30 and 31) * User programmable data format (programmable framing code) * 2 kbytes data cache on-chip to avoid data loss and reduce host CPU overhead * Filtering of packets 30 and 31 WST/NABTS * Choice of clock frequencies, direct-in clock or crystal oscillator * Parallel interface, Motorola, Intel and digital video bus * I2C-bus control * Data transport by digital video bus * Choice of programmable interrupt, DMA or polling driven * Data type selectable video line by video line, with Vertical Blanking Interval and Full Field mode 3 QUICK REFERENCE DATA SYMBOL VDD IDD Vsync(p-p) Vi(CVBS)(p-p) fxtal Tamb Note 1. Selectable: 12, 13.5, 15 or 16 MHz. 4 ORDERING INFORMATION PACKAGE TYPE NUMBER NAME SAA5284GP QFP44 DESCRIPTION plastic quad flat package; 44 leads (lead length 2.35 mm); body 14 x 14 x 2.2 mm VERSION SOT205-1 supply voltage supply current sync voltage (peak-to-peak value) input voltage on pin CVBS0 and CVBS1 (peak-to-peak value) crystal frequency; see note 1 operating ambient temperature PARAMETER MIN. 4.5 - 0.1 0.7 - -20 TYP. 5.0 72 0.3 1.0 12.0 - MAX. UNIT 5.5 95 0.6 1.4 - +70 V mA V V MHz C 2 GENERAL DESCRIPTION The SAA5284 is a Vertical Blanking Interval (VBI) and Full Field (FF) video data acquisition device tailored for application on PC add-in cards, PC mother-boards, set-top boxes and as a SAA5250 replacement. The IC in combination with a range of software modules will acquire most existing formats of broadcast VBI and FF data. These associated software modules are available under licence. Scope is provided for acquiring some as yet unspecified formats. The SAA5284 incorporates all the data slicing, parallel interface, data filtering and control logic. It is controlled either by a parallel interface or I2C-bus. It can output ASCII VBI data as pixels on the digital video bus where no parallel port is available. It is available in a QFP44 package. * Single IC with few external components and small footprint QFP44 package * Optimized for EMC.
1998 Feb 05
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Philips Semiconductors
Objective specification
Multimedia video data acquisition circuit
5 MAIN FUNCTIONAL BLOCKS
SAA5284
7. 12, 13.5, 15 and 16 MHz clock or oscillator options 8. FIFO access to data 9. Interrupt and DMA support 10. Multi-standard parallel interface 11. I2C-bus interface 12. Power-on reset. Figure 1 shows a block diagram of the SAA5284.
1. Input clamp and sync separator 2. Analog-to-digital converter 3. Multi-standard data slicer and clock regenerator 4. Packet filtering; (8 and 4) Hamming correction 5. On-chip data cache 6. Line selectable data type 6 BLOCK DIAGRAM
handbook, full pagewidth
VDDA VSSA VDDX VDDD VSSD3 16 17 6 41 40
RESET
VPOIN0
HREF LLC2 2 43
LLC WR(1) 42
RD(1)
DMACK(1)
VPOIN1 1 38 39
DMARQ 34 36 37
33
35
CS0 CS1 INT RDY(1) SEL0 SEL1 3 DENB A2 to A0(1) D7 to D0(1)
SAA5284
44 31 32 MULTI-STANDARD HOST INTERFACE PACKET BUFFER AND FRONT END CONTROL REGISTERS
CVBS0 CVBS1
15 14 ANALOG SWITCH
10 11 5 30 to 28 20 to 27 8
IREF BLACK
13
12
ANALOG VIDEO TO DATA BYTE CONVERTER (DATA DEMODULATOR)
PACKET FILTERING (e.g. WST packets 30/31) FIFO
I2C-BUS INTERFACE 400 kHz SLAVE
3
SDA
4
SCL
OSCILLATOR AND TIMING 7 8 9
PACKET BUFFER RAM 2 kbyte (45 packets) 18 19
MGG740
OSCOUT OSCGND OSCIN
VSSD1
VSSD2
data path control
(1) Multi-functional pins, see Chapter 7.
Fig.1 Block diagram.
1998 Feb 05
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Philips Semiconductors
Objective specification
Multimedia video data acquisition circuit
7 7.1 PINNING INFORMATION Pinning
SAA5284
36 DMARQ
38 VPOIN0
39 VPOIN1
handbook, full pagewidth
37 DMACK(1)
40 VSSD3
41 VDDD
34 RD(1)
43 LLC2
35 CS0
44 CS1
42 LLC
RESET 1 HREF 2 SDA 3 SCL 4 DENB 5 VDDX 6 OSCOUT 7 OSCIN 8 OSCGND 9 SEL0 10 SEL1 11
33 WR(1) 32 RDY(1) 31 INT 30 A2(1) 29 A1(1)
SAA5284
28 A0(1) 27 D0(1) 26 D1(1) 25 D2(1) 24 D3(1) 23 D4(1)
D6(1) 21
BLACK 12
IREF 13
CVBS1 14
CVBS0 15
VDDA 16
VSSA 17
VSSD1 18
VSSD2 19
D7(1) 20
D5(1) 22
MGG739
(1) Multi-functional pin.
Fig.2 Pin configuration.
7.2
Pin description
Table 1 QFP44 package The IC has a total of 44 pins; many of these are multi-functional due to the multiple host block modes of operation. SYMBOL RESET HREF SDA SCL DENB VDDX OSCOUT OSCIN PIN 1 2 3 4 5 6 7 8 I/O I I I/O I O - O I DESCRIPTION reset IC video horizontal reference signal (digital video mode only) serial data port for I2C-bus, open-drain serial clock input for I2C-bus data enable bar (for external buffers) +5 V supply oscillator output oscillator input
1998 Feb 05
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Philips Semiconductors
Objective specification
Multimedia video data acquisition circuit
SAA5284
SYMBOL OSCGND SEL0 SEL1 BLACK IREF CVBS1 CVBS0 VDDA VSSA VSSD1 VSSD2 D7(1) D6(1) D5(1) D4(1) D3(1) D2(1) D1(1) D0(1) A0(1) A1(1) A2(1) INT RDY(1) WR(1) RD(1) CS0 DMARQ DMACK(1) VPOIN0 VPOIN1 VSSD3 VDDD LLC LLC2 CS1 Note
PIN 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
I/O - I I I/O I I I - - I I I/O I/O I/O I/O I/O I/O I/O I/O I I I O O I I I O I I I - - I I I
DESCRIPTION oscillator ground parallel interface format select 0 parallel interface format select 1 video black level storage; connected to VSSA via 100 nF capacitor reference current input; connected to VSSA via 27 k resistor analog composite video input 1 analog composite video input 0 analog +5 V supply analog ground supply digital ground supply 1 digital ground supply 2 data bus 7/video data output 7 data bus 6/video data output 6 data bus 5/video data output 5 data bus 4/video data output 4 data bus 3/video data output 3 data bus 2/video data output 2 data bus 1/video data output 1 data bus 0/video data output 0 address input 0/video data input 7 address input 1/video data input 6 address input 2/video data input 5 interrupt request ready/DTACK (data acknowledge)/VBI, open-drain Intel bus Write/Motorola bus R/W/video data input 4 Intel bus Read/Motorola bus LDS/video data input 3 chip select 0; active LOW DMA request DMA acknowledge/video data input 2 video data input 0 video data input 1 digital ground supply 3 digital +5 V supply full rate digital video clock input half rate digital video clock input chip select 1; active LOW
1. These pins have two functions, depending on the interface mode.
1998 Feb 05
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Philips Semiconductors
Objective specification
Multimedia video data acquisition circuit
8 8.1 FUNCTIONAL DESCRIPTION Power supply strategy
SAA5284
There are three separate +5 V (VDD) connections to the IC: 1. VDDA supplies the critical noise-sensitive analog front-end sections: ADC and sync separator, to reduce interference from the rest of the front-end 2. VDDX supplies all sections which take standing DC current 3. VDDD supplies the rest of the logic. 8.2 Clocking strategy
The analog video-to-data byte converter is specifically designed to overcome the most commonly found types of distortion of a broadcast video signal. It is also fully multi-standard. The data type to be demodulated is programmable on a line-by-line basis using 4 register bits per line for lines 2 to 23 (PAL numbering), fields 1 and 2, and 4 further bits for all lines combined. 8.6 Packet filtering
The master frequency reference for the IC is a 12, 13.5, 15 or 16 MHz crystal oscillator. The tolerance on the clock frequency is 500 x 10-6 (1.5 kHz). Further specifications of the crystal are given in Table 2. If preferred, an external 12, 13.5, 15 or 16 MHz (1.5 kHz) frequency source may be connected to OSCIN instead of the crystal. 8.3 Power-on reset
If using a slow (e.g. 80C51) microcontroller, it is necessary to reduce the amount of data acquired by SAA5284 before downloading to the microcontroller to avoid it being swamped by unwanted data. Packet filtering is available for this purpose. A common use of this would be to acquire only packet 8/30 in 625-line WST. The packet filter includes optional (8, 4) Hamming correction. 8.7 Packet buffer
The RESET pin should be held HIGH for a minimum of two clock cycles. The reset signal is passed through a Schmitt trigger internally. Direct addressed registers (i.e. those addressed using the A0 to A2 pins) are set to 00H after power-up. All other register bits are assumed to be in random states after power-up. 8.4 Analog switch
This is a 2 kbyte RAM which acts as a buffer for storing received packets. The first 44 bytes are reserved for control information. The rest of the RAM is divided into 44-byte rows (or packets), each holding the data received on one incoming CVBS line. In the case of a WST packet received, the data stored consists of a Magazine and Row-Address Group (2 bytes), followed by the 40 bytes of packet data. When data in other formats than WST is received, this is stored in the packet buffer in the same way. In each case, the data is preceded by two information bytes which record on which line and field the packet was received, and what the data type is. 8.8 FIFO
Register bit selection between two video sources. 8.5 Analog video-to-data byte converter
This section comprises a line and field sync separator, a video clamp, an ADC and a custom adaptive digital filter with DPLL based timing circuit.
FIFO hardware is provided to manage the `read' address for the host processor, i.e. data is read repeatedly from the same 8-bit port, and appears byte-serially in the order of reception. The read address can be reset to the start of the packet buffer (the first 44-byte packet), back to the start of the current packet, or incremented to the start of the next packet.
Table 2
Crystal characteristics PARAMETER series capacitance parallel capacitance resonant resistance ageing adjustment tolerance drift 7 - - - - - - MIN. TYP. 18.5 4.9 - - - - - - 50 5 x 10-6 25 x 25 x 10-6 10-6 MAX. fF pF per year - - UNIT
SYMBOL C1 C2 Rr Xa Xj Xd 1998 Feb 05
Philips Semiconductors
Objective specification
Multimedia video data acquisition circuit
8.9 Host interface 8.10 Interrupt support
SAA5284
The SAA5284 has a multi-standard 8-bit I/O interface. To reduce the amount of host I/O space used, the parallel interface has only 3 address inputs (A0, A1 and A2). An extended addressing (pointer) scheme and the data FIFO are used to allow access to the full set of SAA5284 registers and the full span of the packet buffer. As well as the 8 data I/O lines and 3 address lines, there are the following control signals: RD (read LOW), WR (write LOW), CS0 (chip select LOW), CS1(second chip select LOW), INT (interrupt request), DMARQ (DMA request), DMACK (DMA acknowledge) and RDY (ready). In order to maintain compatibility with Motorola and Intel type buses, two control signals SEL0 and SEL1 are provided to configure the host interface. These signals allow configuration of the host interface to work with the Motorola or Intel style interfaces. The host interface has a digital video mode. Digital video mode may be used to allow the SAA5284 to pass decoded VBI data into a system using the digital video bus.
The host interface provides comprehensive support for interrupt generation. The interrupt may be programmed to occur when a particular number of packets of VBI data are available in the cache RAM. The interrupts can be further controlled to occur on a specific line in the TV frame. The interrupts can also be self masking if required. 8.11 DMA support
Burst and demand mode DMA are supported. In burst mode, the number of packets to transfer can be defined. An interrupt can be generated when DMA is finished. This can be self masking. 8.12 I2C-bus interface
The I2C-bus interface functions as a slave receiver or transmitter at up to 400 kHz. The I2C-bus address is selectable as 20H or 22H. All functionality is available using the I2C-bus although with a slower data transfer speed. It is possible to use the I2C-bus in all modes.
9 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDD VI(max) VO(max) IIOK IO(max) Tstg Tamb PARAMETER supply voltage (all supplies) input voltage (any input) output voltage (any output) DC input or output diode current output current (any output) storage temperature operating ambient temperature MIN. -0.3 -0.3 -0.3 - - - -55 -20 MAX. +6.5 VDD + 0.5 VDD + 0.5 0.25 20 10 +125 +70 V V V V mA mA C C UNIT
VDDD-DDA-DDX supply voltage difference between VDDD, VDDA and VDDX
10 QUALITY & RELIABILITY In accordance with "SNW-FQ-611-E".
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Philips Semiconductors
Objective specification
Multimedia video data acquisition circuit
11 CHARACTERISTICS Tamb = -20 to +70 C; VDD = 4.5 to 5.5 V; unless otherwise specified. SYMBOL Power supply VDDn IDD(tot) IDDD IDDA Vsync(p-p) Vburst(p-p) Vi(vid)(p-p) supply voltage total supply current digital supply current analog supply current 4.5 - - - 5.0 72 32 40 PARAMETER CONDITIONS MIN. TYP.
SAA5284
MAX.
UNIT
5.5 95 42 53
V mA mA mA
Inputs CVBS0 and CVBS1 sync voltage (peak-to-peak value) colour burst voltage (peak-to-peak value) video input voltage (peak-to-peak value) 0.1 0 0.7 0.29 - 1.5 2.5 - - -0.3 2.0 Vi = 0 to VDD -10 - -0.5 3.0 Vi = 0 to VDD VIL(min) to VIH(max); fi(SCL) = 100 kHz VIL(min) to VIH(max); fi(SCL) = 400 kHz ti(f) fi(SCL) CL input fall time input clock frequency load capacitance VIL(max) to VIH(min); fi(SCL) = 100 kHz VIL(max) to VIH(min); fi(SCL) = 400 kHz -10 50 50 50 50 0 - 0.3 0.3 1.0 0.46 - 1.8 5.0 - 0.6 0.4 1.4 0.71 250 2.1 - 10 - V V V V V k pF
Vi(data)(p-p) teletext data input voltage (peak-to-peak value) Zsource Vi(sw) Zi Ci Input IREF RIREF VIL VIH ILI Ci Input SCL VIL VIH ILI Ci ti(r) LOW-level input voltage HIGH-level input voltage input leakage current input capacitance input rise time external resistor to VSSA LOW-level input voltage HIGH-level input voltage input leakage current input capacitance source impedance input switching level of sync separator input impedance input capacitance
27 - - - - - - - - - - - - - -
k
Inputs RESET, HREF, SEL0, SEL1, A0, A1, A2, WR, RD, CS0, CS1, DMACK, VPOIN1, VPOIN0, LLC and LLC2 +0.8 +10 10 V A pF VDD + 0.5 V
+1.5 +10 10 1000 300 300 300 400 400
V A pF ns ns ns ns kHz pF
VDD + 0.5 V
1998 Feb 05
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Philips Semiconductors
Objective specification
Multimedia video data acquisition circuit
SAA5284
SYMBOL
PARAMETER
CONDITIONS
MIN. -0.5 3.0 - - - - - - - - - - - -
TYP.
MAX.
UNIT
Input/output SDA (open-drain) VIL VIH ILI Ci ti(r) ti(f) VOL to(f) CL CBLACK VIL VIH ILI Ci VOL VOH CL to(r) to(f) VOL VOH CL to(r) to(f) VOL CL to(r) to(f) LOW-level input voltage HIGH-level input voltage input leakage current input capacitance input rise time input fall time LOW-level output voltage output fall time load capacitance VIL(min) to VIH(max); fi(SCL) = 100 kHz VIL(min) to VIH(max); fi(SCL) = 400 kHz VIL(max) to VIH(min); fi(SCL) = 400 kHz IOL = 3 mA IOL = 6 mA between 3 and 1.5 V; IOL = 3 mA 50 50 50 0 0 50 - - -0.3 2.0 VIN = 0 to VDD IOL = +1.6 mA IOH = -0.2 mA 0.6 to 2.2 V 2.2 to 0.6 V -10 - 0 2.4 - - - VI = 0 to VDD +1.5 +10 10 1000 300 300 300 0.4 0.6 250 400 - V A pF ns ns ns ns V V ns pF VDD + 0.5 V
-10
VIL(max) to VIH(min); fi(SCL) = 100 kHz 50
Input/output BLACK storage capacitance to VSSA LOW-level input voltage HIGH-level input voltage input leakage current input capacitance LOW-level output voltage HIGH-level output voltage load capacitance output rise time into CL output fall time into CL LOW-level output voltage HIGH-level output voltage load capacitance output rise time into CL output fall time into CL LOW-level output voltage load capacitance output rise time into CL output fall time into CL 0.6 to 2.2 V 2.2 to 0.6 V 0.6 to 2.2 V 2.2 to 0.6 V 100 - - - - - - - - - - - - - - - - - - nF
Inputs/outputs D7 to D0 +0.8 +10 10 0.4 VDD tbf tbf tbf V A pF V V pF ns ns VDD + 0.5 V
Outputs INT, DENB and DMARQ IOL = +1.6 mA IOH = -0.2 mA 0 2.4 - - - 0.4 VDD tbf tbf tbf V V pF ns ns
RDY (open-drain); note 1 IOL = +1.6 mA 0 - - - 0.4 tbf tbf tbf V pF ns ns
1998 Feb 05
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Philips Semiconductors
Objective specification
Multimedia video data acquisition circuit
SAA5284
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
I2C-bus timings (see note 2 and Fig.8) fi(SCL) tLOW tHIGH tSU;DAT tHD;DAT tSU;STO tBUF tHD;STA tSU;STA tr tf Notes 1. ESD protection of this pin falls below the Philips General Quality Specification (GQS). Therefore it is recommended that a diode is connected from pin RDY to VDDD. 2. The I2C-bus interface pins SDA and SCL may pull the data and clock lines below 3 V while the digital power supply VDDD is in the range 0.4 to 0.8 V. SCL input clock frequency SCL LOW time SCL HIGH time data set-up time data hold time set-up time STOP condition bus free time hold time START condition fi(SCL) = 100 kHz fi(SCL) = 400 kHz fi(SCL) = 100 kHz fi(SCL) = 400 kHz fi(SCL) = 100 kHz fi(SCL) = 400 kHz fi(SCL) = 100 kHz fi(SCL) = 400 kHz fi(SCL) = 100 kHz fi(SCL) = 400 kHz fi(SCL) = 100 kHz fi(SCL) = 400 kHz fi(SCL) = 100 kHz fi(SCL) = 400 kHz fi(SCL) = 100 kHz fi(SCL) = 400 kHz set-up time repeated START fi(SCL) = 100 kHz fi(SCL) = 400 kHz rise time (SDA and SCL) fall time (SDA and SCL) fi(SCL) = 100 kHz fi(SCL) = 400 kHz fi(SCL) = 100 kHz fi(SCL) = 400 kHz 0 0 4.7 1.3 4.0 0.6 250 100 0 0 4.7 0.6 4.7 1.3 4.0 0.6 4.7 0.6 - - - - - - - - - - - - - - - - - - - - - - - - - - 100 400 - - - - - - - - - - - - - - - - 1000 300 300 300 kHz kHz s s s s ns ns s s s s s s s s s s ns ns ns ns
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Philips Semiconductors
Objective specification
Multimedia video data acquisition circuit
12 TIMING
SAA5284
handbook, full pagewidth
t0 A2 to A0 t1 D7 to D0 3-state t3 CS0 or CS1 t7 RD t5 RDY
MGK145
valid address t2 valid data t4 3-state
t6
A(1)
B(2)
(1) Event A occurs when RD + CS0 + CS1 = 0 (boolean). (2) Event B occurs when RD + CS0 + CS1 = 1 (boolean).
Fig.3 Intel mode interface read cycle timing.
Table 3
Intel-mode interface read cycle timing (12 MHz clock) DESCRIPTION minimum cycle time address set-up time before event A address hold time after event B data settling time data hold time after event B time from event A until RDY goes LOW RDY LOW time event B to next event A time 0 0 88 0 83 83 83 MIN. 333 - - 712 - 170 530 - MAX. 833 UNIT ns ns ns ns ns ns ns ns
SYMBOL t0 t1 t2 t3 t4 t5 t6 t7
1998 Feb 05
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Philips Semiconductors
Objective specification
Multimedia video data acquisition circuit
SAA5284
handbook, full pagewidth
t0 A2 to A0 t1 D7 to D0 t3 CS0 or CS1 t7 WR t5 RDY
MGK146
valid address t2 valid data t4
t6
A(1)
B(2)
(1) Event A occurs when WR + CS0 + CS1 = 0 (boolean). (2) Event B occurs when WR + CS0 + CS1 = 1 (boolean).
Fig.4 Intel mode interface write cycle timing.
Table 4
Intel-mode interface write cycle timing (12 MHz clock) DESCRIPTION minimum cycle time address set-up time address hold time data set-up time, note 1 data hold time RDY set-up time RDY LOW time event B to next event A time 0 0 0 0 83 83 83 MIN. 333 - - - - 170 530 - MAX. 833 UNIT ns ns ns ns ns ns ns ns
SYMBOL t0 t1 t2 t3 t4 t5 t6 t7 Note
1. Legacy AT bus PCs may not satisfy this requirement as they are not ISA compatible. An application fix is available in the "SAA5284 Users Guide".
1998 Feb 05
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Philips Semiconductors
Objective specification
Multimedia video data acquisition circuit
SAA5284
handbook, full pagewidth
DMARQ t1 DMACK t3 CS (same signal as DMACK) t2
t4
t5
t6
RD(1) t7 D7 to D0 valid data valid data
MGK147
(1) Read data pipelined, so no RD LOW to data valid set-up time.
Fig.5 Intel mode interface DMA cycle timing.
Table 5
Intel-mode interface DMA cycle timing (12 MHz clock) DESCRIPTION DMARQ to DMACK RD LOW to DMARQ LOW cycle time DMACK to RD active data set-up time data hold time data hold from DMACK HIGH 0 0 252 - 0 83 0 MIN. - 212 - 0 90(1) - 83 MAX. UNIT ns ns ns ns ns ns ns
SYMBOL t1 t2 t3 t4 t5 t6 t7 Note
1. This timing will be up to 3 clock cycles for the first read in DMA transfer.
1998 Feb 05
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Philips Semiconductors
Objective specification
Multimedia video data acquisition circuit
SAA5284
handbook, full pagewidth
t0 A2 to A0 t1 D7 to D0 3-state valid data t3 CS1 or CS0 t7 R/W valid address t2 3-state
LDS t4 DTACK
MGK148
t5
t6
A
(1)
B
(2)
(1) Event A occurs when LDS + CS0 + CS1 = 0 (boolean). (2) Event B occurs when LDS + CS0 + CS1 = 1 (boolean).
Fig.6 Motorola mode interface read cycle timing.
Table 6
Motorola-mode interface read cycle timing (12 MHz clock) DESCRIPTION minimum cycle time address set-up time before event A address hold time after event B data hold time from event B data settling time data valid to DTACK LOW LDS HIGH to DTACK HIGH delay between cycles 0 0 0 88 83 83 83 MIN. 333 - - - 712 170 212 - MAX. 833 UNIT ns ns ns ns ns ns ns ns
SYMBOL t0 t1 t2 t3 t4 t5 t6 t7
1998 Feb 05
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Philips Semiconductors
Objective specification
Multimedia video data acquisition circuit
SAA5284
handbook, full pagewidth
t0 A2 to A0 t1 D7 to D0 3-state valid data t3 CS1 or CS0 t7 R/W t4 LDS t5 DTACK
(1)
valid address t2 3-state
t6
A
B(2)
MGK149
(1) Event A occurs when LDS + CS0 + CS1 = 0 (boolean). (2) Event B occurs when LDS + CS0 + CS1 = 1 (boolean).
Fig.7 Motorola mode interface write cycle timing.
Table 7
Motorola-mode interface write cycle timing (12 MHz clock) DESCRIPTION minimum cycle time address set-up time before event A address hold time after event B data hold time from event B data set-up time DTACK set-up time LDS HIGH to DTACK HIGH delay between cycles 0 0 0 0 - 83 83 MIN. 333 - - - - 212 212 - MAX. 417 UNIT ns ns ns ns ns ns ns ns
SYMBOL t0 t1 t2 t3 t4 t5 t6 t7
1998 Feb 05
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Philips Semiconductors
Objective specification
Multimedia video data acquisition circuit
SAA5284
handbook, full pagewidth
tr tHIGH tLOW
tf
SCL tHD;STA tSU;STA
tSU;DAT
tHD;DAT
tSU;STO
SDA
MGG741
tBUF
Fig.8 I2C-bus timing diagram.
handbook, full pagewidth
VPOIN t0 VPOOUT t1 CS0 or CS1 t4 LLC t2 t3
LLC2
MGK150
Fig.9 Digital video mode interface timing.
Table 8
Digital video mode interface timing with 13.5 MHz clock and 27 MHz LLC DESCRIPTION VPOIN set-up time VPOOUT set-up time CS HIGH to VPOOUT 3-state CS LOW to VPOOUT enabled clock qualifier set-up time 4 8 6 9 - MIN. 5 10 10 11 1.1 TYP. 6 22 25 16 - MAX. UNIT ns ns ns ns ns
SYMBOL t0 t1 t2 t3 t4
1998 Feb 05
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Philips Semiconductors
Objective specification
Multimedia video data acquisition circuit
13 APPLICATION INFORMATION 13.1 Hardware application circuit for ISA card 13.3
SAA5284
Software application information
A typical application circuit diagram (for the ISA card application) is shown in Fig.10. 13.2 Hardware application circuit for PCI application
This PCI application is based around the Philips SAA7146 video to PCI bridge IC. SAA7146 has a `Data Expansion Bus Interface' (DEBI) which is an Intel/Motorola style 16-bit parallel interface. This is used to facilitate communications to SAA5284. The application circuit diagram is shown in Fig.11.
PC application software is available providing two levels of interface. At a low level a VxD based driver offers generic packet gathering and buffering. Full support is provided for ISA based applications with facility for PCI based applications. Higher level support is provided by a series of DLLs. These perform normal teletext display generation and page management.
1998 Feb 05
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Philips Semiconductors
Objective specification
Multimedia video data acquisition circuit
SAA5284
handbook, full pagewidth
VDDA = +5 V VDDA 100 nF VSSA = 0 V 75 27 k 100 nF CVBS0 100 nF CVBS1 75 VSSA = 0 V BLACK IREF 16 12
VDDD = +5 V VDDD 41 6 20 21 VDDX D7 D6 D5 D4 D3 D2 D1 D0 A0 A1 A2 INT RDY(2) WR RD DMARQ D7 D6 D5 D4 D3 D2 D1 D0 A0 A1 A2 IRQx I/O RDY IOW IOR
13
22 23
CVBS0
15
24 25
CVBS1
14
26 27
OSCIN 12 MHz(1) 22 pF OSCOUT 22 pF OSCGND SDA SCL HREF LLC LLC2 VPOIN1 VPOIN0
8 28 7 29
SAA5284
9
30 31
3 4 2 42 43 39 38 17 40 18 19 11 10 44 VSSA VSSD3 VSSD1 VSSD2 SEL1
32 33 34 36 37 1 5
DACKx DMACK(3) RESET DENB RESET n.c.
35 SEL0 CS1
CS0
VSSD = 0 V
VSSA = 0 V VSSD = 0 V B9 B8 B7 supply decoupling VDDA VDDD +5 V B6 n.c. B5 B4 B3 100 nF 10 F 100 nF 10 F B2 19 18 17 16 15 14 13 12
B1 11 9
B0 1 I0 I1 I2 I3 I4 I5 I6 I7 AEN A3 A4 A5 A6 A7 A8 A9
ADDRESS DECODER e.g. PLUS153 or 74 SERIES LOGIC
2 3 4 5 6 7 8
VSSA
VSSD
0V
10 GND VSSD = 0 V
20 VCC VDDD = 5 V
MGG742
(1) Option of 13.5, 15 and 16 MHz or direct feed from external clock. (2) A diode to VDDD is recommended for ESD protection. (3) Pin DMACK must be connected to VDDD if DMA is not used.
Fig.10 Application circuit diagram for ISA card.
1998 Feb 05
19
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 1998 Feb 05
VDDA = +5 V VDDA 100 nF VSSA = 0 V 75 27 k 100 nF CVBS0 100 nF CVBS1 75 VSSA = 0 V BLACK IREF 16 12 13 CVBS0 15 CVBS1 14 OSCIN 12 MHz(1) 22 pF OSCOUT 22 pF OSCGND SDA supply decoupling VDDA VDDD +5 V SCL HREF LLC 100 nF 10 F 100 nF 10 F LLC2 VPOIN1 VSSA VSSD 0V VPOIN0 7 8
Philips Semiconductors
VDDD = +5 V VDDD 41 6 20 21 22 23 24 25 26 27 28 29 VDDX D7 D6 D5 D4 D3 D2 D1 D0 A0 A1 1Q 2Q 16 15 2 3 1D 2D XAD7 XAD6 XAD5 XAD4 XAD3 XAD2 XAD1 XAD0
SAA5284
9 3 4 2 42 43 39 38 17 40 18 19 11 10 44 VSSA VSSD3 VSSD1 VSSD2 SEL1 VSSA = 0 V VSSD = 0 V
handbook, full pagewidth
Multimedia video data acquisition circuit
SAA7145 SAA7146
DEBI PORT 132 131 130 129 126 125 124 123
74HCT75
30 A2 3Q 10 13 LE 6 3D 4D 47 LE
20
35 31 32 33 34 36 37 1 5
CS0 INT RDY WR RD DMARQ DMACK RESET DENB
ALE XIRQ RDY WRN RDN
114 118 117 116 115
n.c. VDDD n.c.
5 k VDDD RESET 23
VSSD = 0 V
SEL0 CS1
MGG744
Objective specification
SAA5284
(1) Option of 13.5, 15 and 16 MHz or LLC2 from the SAA7111 if in 13.5 MHz mode.
Fig.11 Application circuit diagram for PCI application.
Philips Semiconductors
Objective specification
Multimedia video data acquisition circuit
14 PACKAGE OUTLINE QFP44: plastic quad flat package; 44 leads (lead length 2.35 mm); body 14 x 14 x 2.2 mm
SAA5284
SOT205-1
c
y X
33 34
23 22 ZE
A
e E HE wM bp pin 1 index 44 1 11 ZD bp D HD wM B vM B 12 detail X L Lp A A2 A1 (A 3)
e
vM A
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2.60 A1 0.25 0.05 A2 2.3 2.1 A3 0.25 bp 0.50 0.35 c 0.25 0.14 D (1) 14.1 13.9 E (1) 14.1 13.9 e 1 HD 19.2 18.2 HE 19.2 18.2 L 2.35 Lp 2.0 1.2 v 0.3 w 0.15 y 0.1 Z D (1) Z E (1) 2.4 1.8 2.4 1.8 7 0o
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT205-1 REFERENCES IEC 133E01A JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 95-02-04 97-08-01
1998 Feb 05
21
Philips Semiconductors
Objective specification
Multimedia video data acquisition circuit
15 SOLDERING 15.1 Introduction
SAA5284
If wave soldering cannot be avoided, for QFP packages with a pitch (e) larger than 0.5 mm, the following conditions must be observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 15.4 Repairing soldered joints
There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). 15.2 Reflow soldering
Reflow soldering techniques are suitable for all QFP packages. The choice of heating method may be influenced by larger plastic QFP packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For more information, refer to the Drypack chapter in our "Quality Reference Handbook" (order code 9397 750 00192). Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 50 and 300 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. 15.3 Wave soldering
Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
Wave soldering is not recommended for QFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. CAUTION Wave soldering is NOT applicable for all QFP packages with a pitch (e) equal or less than 0.5 mm.
1998 Feb 05
22
Philips Semiconductors
Objective specification
Multimedia video data acquisition circuit
16 DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
SAA5284
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 17 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 18 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
1998 Feb 05
23
Philips Semiconductors - a worldwide company
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For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1997
Internet: http://www.semiconductors.philips.com
SCA53
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
655102/00/02/pp24
Date of release: 1998 Feb 05
Document order number:
9397 750 02768

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